1. IN A LOGICAL ADDER THE COMBINATION OF INPUT MEANS FOR SUPPLYING VOLTAGE SIGNALS REPRESENTATIVE OF AUGEND AND ADDEND DIGITS, OUTPUT MEANS THE VOLTAGE STATES OF WHICH REPRESENT SUM DIGITS, SAID INPUT AND OUTPUT MEANS BEING DIVIDED INTO A PLURALITY OF FIRST LEVEL GROUPS, EACH OF SAID FIRST LEVEL GROUPS IN TURN BEING DIVIDED INTO A PLURALITY OF SECOND LEVEL GROUPS, EACH OF THE SECOND LEVEL GROUPS THEREBY HAVING INPUT MEANS FOR SUPPLYING VOLTAGE SIGNALS REPRESENTATIVE OF A SUBAUGEND AND A CORRESPONDING SUBADDEND, AND OUTPUT MEANS THE VOLTAGE STATE OF WHICH REPRESENTS TRUE SUBSUM DIGITS; FIRST MEANS ASSOCIATED WITH EACH OF SAID SECOND LEVEL GROUPS RESPONSIVE TO SAID SUBAUGEND AND SUBADDEND INPUT MEANS FOR PRODUCING VOLTAGE SIGNALS REPRESENTATIVE OF A FIRST SUBSUM AND A FIRST GROUP CARRY OUTPUT, SAID FIRST GROUP CARRY OUTPUT BEING GENERATED SIMULTANEOUSLY FOR ALL GROUPS; SECOND MEANS ASSOCIATED WITH EACH OF SAID SECOND LEVEL GROUPS RESPONSIVE TO SAID SUBAUGEND AND SUBADDEND INPUT MEANS FOR PRODUCING SIMULTANEOUSLY WITH SAID FIRST MEANS VOLTAGE SIGNALS REPRESENTATIVE OF A SECOND SUBSUM HIGHER BY ONE THAN SAID FIRST SUBSUM AND FOR PRODUCING VOLTAGE SIGNALS REPRESENTATIVE OF A SECOND GROUP CARRY OUTPUT, SAID SECOND GROUP CARRY OUTPUT BEING GENERATED SIMULTANEOUSLY FOR ALL GROUPS; MEANS ASSOCIATED WITH EACH OF SAID FIRST LEVEL GROUPS RESPONSIVE TO THE GROUP CARRY OUTPUT SIGNALS FROM SECOND LEVEL GROUPS HAVING DIGITAL POSITIONS OF LOWER DIGITAL ORDER FOR PRODUCING A RESPECTIVE CARRY INPUT SIGNAL INTO EACH FIRST LEVEL DIGITAL GROUP; AND MEANS WITHIN EACH OF SAID FIRST LEVEL GROUPS RESPECTIVELY RESPONSIVE TO SAID CARRY INPUT SIGNALS AND TO THE GROUP CARRY OUTPUTS FROM SECOND LEVEL GROUPS WITHIN THE RESPECTIVE FIRST LEVEL GROUP WHICH HAVE DIGITAL POSITIONS OF LOWER DIGITAL ORDER TO SELECT THE SUBSUM FOR EACH SECOND LEVEL GROUP CORRESPONDING TO THE TRUE SUBSUM.

g- 3 o. J. BEDRIJ. 3,100,835
SELECTING ADDER Filed Jan. 6, 1960 7 Sheets-Sheet 3 M 'A3 A5 B4 B3 B5 i f 0 0 FIG. 4a 0 n o o (SHEETiOFZ) A B V A1 AND 2 B V' AND "2 1 '2 AND OR V. S4n
5 B V AND 9 AND OR V A I B4 V' AND A 4 AND J I: V
Aug. 13, 1963 Filed Jan. 6, 1960 FIG. 4b
(SHEET 2 OF 2) O. J. BEDRIJ SELECTING ADDER 7 sheets-sheet 4 Aug. 13, 1963 o. J. BEDRIJ 3,100,835
SELECTING ADDER Filed Jan. 6, I960 '7 Sheets-Sheet 6 FIG. 7
'1 I- I I ,--2o2 l I ANDI AND AND I I I I I I v v I v v I 's s 's J 2 2 i i "203 I I 201 I v I v -I vII v v I I I I I INDICATOR O. J. BEDRIJ SELECTING ADDER Aug. 13, 1963 7 Sheets-Sheet 7 Filed Jan. 6, I 1960 AND I l I i F|G.8b
United States Patent 3,1ilil,835 SELECTENG ADDER Orest .l. Bedrij, l oughhcepsie, N321, assignor to Internet This invention relates to digital computers and more particularly to digital adders.
In an elementary digital adder, the time required to add two numbers having a large number of digits is dependent upon the time required for the propagation of carries from the least significant to the most significant digit. The generation of sums for each digital position proceeds sequentially from the least significant to the most significant position, each sum being generated only after a signal is present which indicates whether or not the addition in the previous digital positions produced a carry.
More advanced schemes provide means for increasing the speed of the addition. The system described in The National Bureau of Standards Circular 591 shows a scheme whereby the system first determines if there is a carry into each of a plurality of digital positions, and then simultaneously generates the sum of each of these digits based upon the previous determination as to the existence of a carry into each digital position. However, when applied to numbers which have a large number of digital positions, the speed of such systems remains limited due to the limitations inherent in the physical circuits which are available. Circuits of the above type which are designed to add numbers which have a large number of digital positions essentially break the digital positions of the numbers to he added into groups. The carries within each group are genenated simultaneously; however, the various groups operate sequentially.
The systems herein described overcome the problem of carry propagation delay by dividing the digital positions of the addend and augend into a plurality of groups, each group thereby having a subaugend and corresponding subaddend. During the first step in the operation, the subaugends and corresponding subaddends tare simultaneously added twice, thereby producing two subsums. One addition assumes that there was a carry into each group, and the second addition assumes that there was no carry into each group. During the second step in the operation, the correct subsums for all groups are simultaneously selected.
It is the object of the present invention to provide a faster adder circuit.
A further object is to provide a faster adder circuit using a minimum number of components.
A further object is to provide an improved adder check circuit.
A further object is to provide an adder circuit which can readily be broken into units for packaging.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more pnaticular description of the preferred embodiments of the invention, as illustnated in the accompanying drawings.
In the drawings:
FlG. 1 is a block diagram of a simplified embodiment of the invention.
FIG. 2 is a block diagram showing the overall organization of a preferred embodiment of the invention.
FIG. 3 is a block diagram showing the general organization of one of the first level groups, shown in FIG. 2.
FIGS. 4a and 4b are circuit diagrams of a five bit adder module shown in FIG. 3.
FIGS. 5a to 5e are circuit diagrams of the module carry input circuits shown in PEG. 3. l
2 FIG. 6 is a circuit diagram of the sum gates shown in FIG. 3.
FIG. 7 is a circuit diagram of one of the carry loolo ahead circuits shown in FIG. 2.
FIGS. 8a to 8e are circuit diagrams of the group canry input circuits shown in FIG. 2.
FIG. 9 is a circuit diagram of a checking circuit.
The invention will first the described in a general way with reference to the simplified embodiment shown in FIG. 1. With this simplified embodiment a fifteen di it addend A 15 can be added to a fifteen digit auge-nd B to}? thereby producing a fifteen digit true sum S to Provision is also made for a carry input C to the least significant digital position. The carry C is known in the art as an end around carry and it is used when adding a negative number, which is in complement form, to a positive number.
The di its of the numbers to be added are broken down into groups. In the embodiment shown in FIG. 1, the fifteen bit augend and the fifteen ibit addend are broken into three groups, a, b and 0, each group thereby having a sub augend, a subaddend, and \a true subsun'l. of five digital positions.
in order to facilitate an understanding of the invention, the following descriptive numbering scheme will be used throughout. Augend, addend, and true sum digits will respectively be designated by an A, B or S, followed by a subscript to designate a digital position (erg, 8 for the twelfth true sum digit). Carries will be designated by a capital C followed by a subscript to designate which digital position generated the carry (6%., C is a carry out of the fifth digital position). An S or C which is followed by a y or n in the subscript indicates that such sum or carry digit is only provisional and that it has been generated under some assumption. The subscript y indicates an assumption that there was a carry into some previous digital position and the subscript It indicates an assumption that there was not a carry into some previous digital position. As will be seen later the assumption relates to the presence of a carry into the lowest order digital positron of the minor digital group under consideration. The absence of an n or y in the subscript indicates that it is the true sum or true carry.
In FIG. 1 blocks little, iiliib, 1610, 1926!, 162 b and 1622c each represent five bit conventional logical adders. Each adder may consist, for example, of five sequentially connected full adders of the type shown within the dotted lines in FIGS. 4l or 4-2, on pages 84 and 85, respectively, of Arithmetic Operations in Digital Computers by R. K. Richards, D. Van Nostrand Company, Inc. New York, 1955.
All the adders 161a, b and c and 1452a, b and c operate simultaneously, adders 1931a, Nib, and little operate with no carry input to the least significant digital positron of their respective groups, While adders 1d2a, 19217 and 1620 operate with a forced carry input to the least significant digital position of the respective groups. The adders 191a, iilib and itllc respectively produce sun1 d1g1ts in to 5m S611 to 10:1 and S1111 to 15n and Output carries 5n, C and C Likewise adders 102a, 1021; and 1020 respectively produce sum digits S to 8 to my and S to my and output carries C C and C From the first group, either sum digits S to 5y or sum digits S to are gated by AND gates led through GR circuits 1&5 to the output, depending upon whether or not there is a carry input C into the first group. Likewise either digits S my or digits S to from the second group and digits S to my or digits S to from the third group are gated to the output depending upon whether C and C respectively are present. Circuits 10 i and combined are identical to circuits 122 of the second embodiment which are shown in FIG. 6 and which will be explained in detail later.
The carries C C C and C are produced by circuits 1030, 103b, 1030 and 103d. Circuit 103a merely examines whether or not there is a carry input C to the circuit and it then accordingly generates output C or Circuit 103d is identical to circuit 121d shown in FIG. 5.
The operations of the adders 101 and 102 proceed simultaneously and likewise, all of the circuits 103 operate simultaneously. (Note, where a plurality of similar circuits areeach identified by a numeral followed by a different lower case letter, a reference to the numeral is a reference to all such circuits.) The addition proceeds essentially in two steps, first each subaddend and subaugend is added twice, one addition by adders 102 assuming that there was a carry into each group and the second addition by adders 101 assuming that there was no carry into each group. In the second step the true subsum for each group is gated to the output by circuits 103 'and 104 depending upon whether or not there actually was a carry into that group. If a special type of adder is used the output carries C C C C C and C can be produced more quickly than the sum digits S to and S to and hence circuits 103 can start operating before the sum digits are produced. This will be'more thoroughly and clearly explained later with reference to the preferred embodiment.
The basic circuit arrangement shown in FIG. 1 could be extended to include any number of groups; however, the control circuits 103 for circuits beyond the fourth or fifth level would become exceedingly complex and costly, hence, a multilevel system, an example of which is shown by the preferred embodiment, is preferable.
A second and preferred embodiment of the invention showing a multilevel system as applied to a one hundred digit adder is shown in FIGS. 2, 3, 4, 5, 6, 7, 8 and 9. The digital positions of the addend A to of the augend B1 t 100 and 0f the Sum S1 t 100 are into four major digit groups, 110a, 110b, 1100 and 110d (FIG. 2); each major digit group is in turn divided into five minor digit groups 111a, 111b, 1110, 1110! and 1112 (FIG. 3), each minor digital group having five digital positions. These major and minor digit groups may also be referred to as first and second level groups, respectively.
FIG. 2 shows the general organization of the four major digit groups 110a, 1101:, 1100 and 110d, each major digit group 110 having components 115, 116 and 117. FIG. 3 shows the general organization of each circuit 115. Each circuit 115 has five sets (a, b, c, d and e) of components 120, 121, and 122 (corresponding to the five minor digit groups).
The circuit shown in FIG. 3 is the circuit 115a for major digit group 110a; however, the other circuits 115b, 1150 and 115d have circuits identical to the one shown here for group 115a. FIGS. 8a to 80 show the organization of circuits 1160, 116b, 1160 and 116d. FIG. 7 shows the organization of circuit 117a. Circuits 117b, 1170 and 11701, are identical to circuit 117a. FIGS. 4a and 4b show the organization of a circuit 120a. The circuits 120b, 1200, 120d and 120:: are identical to circuit 120a.
I FIGS. 5a to 5e show the organization of each of the circnits 121 and FIG. 6 shows the organization of circuits 122.
In general, each of the major digit groups operates as follows: the five circuits 120, each of which is associated with a particular set of five digital positions (a minor group) generates two sets of sum digits, S and S for the respective minor group of digital positions, one set of sum digits S being generated under the assumption that there was no carry into the least significant digital position of the respective minor group of digital positions, and the second set' of sum digits S being generated under the assumption that there was a carry into the least significant digital position of the respective minor digit group. The circuits 120 also produce outputs C and C which indicate whether there is a carry out of the highest digital position of the respective minor digit group. Circuits 121 examine the carry input to the major digit group and the C and C carry outputs from all the minor digit groups of lower digital order in the respective major group, and produce a carry signal indicative as to whether or not there actually should be a carry into the lowest digital order of the associated minor digit group; said By way of analogy to the first embodiment of the invention which is shown in FIG. 1 circuits 120 perform the combined function of circuits 101 and 102.
Each circuit 120 operates on five'digital positions, e.g. A to 5 and B and makes available two sums, e.g. S to 5y and Si to one of which, i.e. S to is produced assuming that there was a carry into that minor group and the other sum, i.e. S to being produced on the assumption that there was not a carry into that minor group. Circuits 120 also produce two other outputs C and C These outputs are equivalent to the C and C carry outputs of adders 101 and 102 in FIG. 1.
The circuits 1-20 comprise the shown plurality (FIGS. 4a and 4b) of logical AND and OR blocks connected according to the Boolean equations given below.. The AND and OR blocks shown may be of the well known type described in Digital Computer Components and Circuits, by R. K. Richards, pages 178-186, D. Van Nostrand Co., Inc., 1957.
Note, the symbol 1 denotes the exclusive OR function. That is, an output is generated if either, but not both of the input signals are present.
carriers C and C would be produced only after all of the digital sums S to and S to had been produced, since in a conventional adder the sum and carry for each successive digital position is produced only after the addition of the previous digit is complete.
If the time required for one logical block to change state after a signal is applied is designated by T, the time after the A to 5 and B to 5 inputs are activatedand before the carries C and (3 are available is 3T. The time after A and B signals are applied and before all the S and 3,, digits are available is 81. Hence, the operation of circuits 121 which determine whether circuit 122 should gate the S digits or the S digits to the output, can start operating before the sum digits S and S are available.
Circuits 121 which are shown in FIGS. 5a to 5e examine the carry outputs from all the previous adders and determine which sum digits S or 8,, should be gated to the output. The circuits 121a, 121b, 1210, 121d and 121e comprise the shown plurality of logical AND and OR gates interconnected in accordance with the following Boolean equations wherein:
C represents the carry into the lowest order digital position of the major group under consideration (e.g. in FIG. 3 we are showing major group 110a, hence, the carry input is C If we were showing the second group, the carry input would be C etc.).
CO=CO It is realized that certain functions in the equations for S S (i and C are common to each equation and that a certain number of components could be saved by generating these functions only once; however, to facilitate the understanding and explanation of the invention, each of the circuits is described separately.
Circuit 121a is merely an inverter driver which has two outputs, the first output is logically identical to the input and the second output is the logical inverse of the input.
The circuitry for circuits 121 in the other major digital groups is identical to the circuitry here shown for major group 110a; however, the digital position designations would naturally be different. The designation for major group 1111b would each be increased by twenty-five positions from that shown here, for major group llllc each designation would be increased by fifty digital positions from that shown here, and for major group 1160!, each designation would be increased by seventy-five digital positions from that shown here. The OR logic blocks shown in FIGS. b, 5c, 5d and 5e perform a conventional OR function, that is, produce outputs C C C and C respectively, whenever at least one of the inputs is present. Further, each of these OR logic blocks incorporates additional well-known elements for producing a second output inverse to the normal output (i.e., C (1 0 and 655, respectively). It is to be noted that the logic block of PEG. 5a receives only a single input, but since it produces the same logical result as the corresponding blocks in FIGS. Sb-Se, it is labeled as an OR block in order to preserve consistency in the sequence of logical functions shown in FIGS. 512-58.
Each circuit 122 (FIG. 6) has two AND circuits followed by an OR circuit for each digital position whereby either the 5,, or S sum for the particular digital position can be gated to the output in accordance with whether the signal from the associated circuit 121 is C or Thus far the discussion has been limited to one representative major digital group (i.e., 110a). The general scheme thus far shown, an example of which is represented by the organization of each major digital group and likewise by the scheme described in the first embodimerit, could theoretically be extended to cover any number of digital positions; however, the circuits 121 would become exceedingly costly and complex.
One alternative would be to have a plurality of major digit groups which operate sequentially, the internal workings of each major digit group operating as hereinbefore described for major group a. However, a faster scheme is achieved by applying the principle of this invention on a two level basis as shown by the preferred embodiment. With reference to FIG. 2, each of the circuits for major digit groups 110a, 110b, 1100 and 110d operate as hereinbefore described for circuits 115a.
During the first step in the operation, all of the circuits 1243 in each major group operate simultaneously, thereby first producing outputs C and C and later producing outputs S and S Since circuits 121 of the major groups illiia, 11%, 1160 and HM cannot operate until the respective signals C C C and C are present, during the second step in the operation the circuits 117 and 116 simultaneously produce outputs C C C and C For example, circuits 117a (FIG. 7) examine outputs C53: Q1031 ltiy: 'CZOY: C253]: C511 C1311! C1511! C2011: C25! of the associated major group 116a and produce outputs X and Z,,. The circuits 116 (FIG. 8) examine the C X and Z outputs and produce the respective carries, C 5, C and C Each circuit 117 comprises a plurality of AND and OR circuits connected in accordance with the following Boolean equations:
- 20y 25y 15n+ 25y 20n+ 25n a= 5y 1Oy 15y 20y 25y All of the circuits 117 are identical. Circuits 116 (FIGS. 8a to 86) comprise a plurality of AND and OR circuits connected in accordance with the following Boolean equations:
Circuit 116a may in reality be merely a direct connection, however, for consistency, a block marked 116a is shown.
During the third step in the operation each circuit 121 for each major digit group selects the correct subsums F or 8,, for each minor group as hereinbefore described for group 110a.
For operation on numbers with a greater number of digital orders the principle herein described could be extended to three or more levels.
In certain applications of this system, the end around carry C into the lowest order digital position will never occur; hence, there will be no need for adder 102a.
The checking feature (FIG. 9) of the invention will be explained with reference to the embodiment shown in FIG. 1; however, the checking feature is equally applicable to the second embodiment. Remembering that the difference between sums S and S is that the first sum 8,, was generated without a carry into the lowest order digital position and that the second sum was gen erated with a carry into the lowest order digital position,
it is seen that the difference between the two sums for each minor group (e.g. S to and S to should be ,one. Hence, the checking circuit essentially adds one to the S sum and compares the result with S sum. The indicator cincuit 201 gives an indication of any discrepancy. Circuits 202 are conventional logical adders comprising a plurality of logical AND and OR circuits ano e-ea interconnected in accordance with the following Boolean equations:
Circuits 203 are conventional NOT AND circuits, one for each digital position, which give an output if there is a difierence between the S and S signals.
The circuits shown herein are merely illustrative and the number of digital positions per group, the number of groups, and the number of levels of groups could be changed to meet special requirements without departing from the spirit of the invention disclosed and claimed herein.
A further advantage of the adder disclosed herein is its adaptability to the packaging techniques used in digital computers. Each five bit module can be placed on one or two printed circuits thus providing a readily distinct unit for packaging.
While the invention has been-particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
1 claim:
1. In a logical adder the combination of input means for supplying voltage signals representative of augend and addend digits, output means the voltage states of which represent sum digits, said input and output means being divided into a plurality of first level groups, each of'said first level groups in turn being divided into a plurality of second level groups, each of the second level groups thereby having input means for supplying voltage signals representative of a subaugend and a corresponding subaddend, and output means the voltage state of which represents true subsum digits; first means associated with each of said second level groups responsive to said subaugend and subaddend input means for producing voltage signals representative of a first subsum and a first group carry output, said first group carry output being generated simultaneously for all groups; second means associated with each of said second level groups responsive to said subaugend and subaddend input means for producing simultaneously with said first means voltage signals representative of a second subsum higher by one than said first subsum and for producing voltage signals representative of a second group carry output, said second group carry output being generated simultaneously for all groups; means associated with each of said first level groups responsive to the group carry output signals from second level groups having digital positions of lower digital order for producing a respective carry input signal into each first level digital group; and means within each of said first level groups respectively responsive to said carry input signals and to the group carry outputs from second level groups within the respective first level group which have digital positions of lower digital order to select the subsum for each second level group corresponding to the true subsum.
2. In a logical adder the combination of input means for supply voltage signals representative of augend and addend digits, output means the voltage states of which represent sum digits, said input and output means being successively subdivided a plurality of times thereby forming groups within groups in a plurality of size levels, the smallest groups thereby having input means for supplying voltage signals representative of a subaugend and a corresponding subaddend and output means the voltage states of whichirepresent true subsum digits, first means associated with each of the smallest groups responsive to said subaugend and subaddend input means for producing voltage signals representative of a first subsum and a first group carry output, second means associated with each of the smallest groups responsive to said subaugend and subaddend input means for producing simultaneously with said first means voltage signals representative of a second subsum higher by one than said first subsum and for producing voltage signals representative of a second group carry output; means for each group in each level, except the lowest, respectively responsive to the group carry outputs from lowest level groups respectively having digital positions of lower digital order than the digital positions of the respective group for generating carries into the respective groups in each level except the lowest, said carries being generated simultaneously for groups in like levels; and means in each group of lowest level groups responsive to the respective group carry input and to group carry outputs of lowest level groups within the respective group having digital positions of lower digital order to select the subsum corresponding to the true subsum for each lowest level digital group.
3. An adder wherein the digital positions of the augend, addend, and sum are divided into a plurality of groups, each of said groups thereby having a subaugend, a corresponding subaddend, and a true subsum, means for generating a first subsum and a first group carry output from each subaugend and corresponding subaddend without a carry into the least significant digital order of each group, means for simultaneously generating a second subsum and a corresponding second group carry output for each subaugend and corresponding subaddend with a forced :carry into the least significant digital order of each group, said group carry outputs being generated simultaneously for all groups, and means for each group directly and simultaneously responsive to the group carry outputs from all groups of lower digital order for selecting the subsums corresponding to the true subsums.
4. In a logical adder, the combination of input means for supplying voltage signals representative of augend and addend digits; output means the voltage states of which represent sum digits, said input and output means being divided into a plurality of major digit groups, each of said major digit groups in turn being divided into a plurality of minor digit groups, each of the minor digit groups thereby having input means for supplying voltage signals representative of a subaugend and a corresponding subaddend and output means the voltage states of which represent true subsum digits; first means associated with each of said minor digit groups responsive to said subaugend and subaddend input means for producing voltage signals representative of a first subsum and a first minor digit group carry output, said first minor digit group carry output being generated simultaneously for all minor digit groups; second means associated with each of said minor digit groups responsive to said subaugend and subaddend input means for producing simultaneously with said first means voltage signals representative of a second subsum higher by one than said first subsum and for producing an associated second minor digit group carry output, said second minor digit group carry output being generated simultaneously for all minor digit groups; means associated with each'of said major digit groups responsive to the minor digit group carry output signals from the respective minor digit groups therein for producing simultaneously from each of said major digit groups a first and a second major digit group carry output, said first major digit group carry output being generated when all of said respective minor digit groups therein produce a second minor digit group carry output, and said second major digit group carry output being generatedwhen the highest order minor digit group within the respective major digit group produces a first minor digit group carry output or when any given minor digit group Within said respective major digit group produces a first minor digit group carry output while all higher order minor digit groups within said respective major digit group relative to said given group produce second minor digit group carry outputs; initial carry input means for producing a voltage signal representative of an initial carry input into the lowest order minor digit group within the lowest order major digit group of said logical adder; means within each of said major digit groups responsive to said major digit group carry output signals from all major digit groups of lower digital order and to-said initial carry input signal for simultaneously generating a true carry input into each respective major digit group; and means associated with each minor digit group respon- 1Q sive to said'true carry input into the associated major digit group and to minor digit group carry outputs of all minor digit groups of lower digital order within the respective major digit group to simultaneously select the subsum for each minor digit group corresponding to the true subsum.
References Cited in the file of this patent UNITED STATES PATENTS Schmitt et a1 Nov. 25, 1958 2,954,168 -Maddox Sept. 27, 1960

Publication number | Publication date | Assignee | Title |
---|---|---|---|

US-2861744-A | November 25, 1958 | Rca Corp | Verification system |

US-2954168-A | September 27, 1960 | Philco Corp | Parallel binary adder-subtracter circuits |

Title |
---|

Publication number | Publication date | Assignee | Title |
---|---|---|---|

EP-0075740-A2 | April 06, 1983 | Siemens Aktiengesellschaft | Circuit de calcul digital et son procédé de fonctionnement |

EP-0075740-A3 | January 29, 1986 | Siemens Aktiengesellschaft | Digitales Rechenwerk und Verfahren zu seinem Betrieb |

EP-0081632-A2 | June 22, 1983 | Kabushiki Kaisha Toshiba | Addierschaltung |

EP-0081632-A3 | January 29, 1986 | Kabushiki Kaisha Toshiba | Adder circuit |

EP-0123921-A2 | November 07, 1984 | Siemens Aktiengesellschaft | Parallelverknüpfungsschaltung mit verkürztem Übertragsdurchlauf |

EP-0123921-A3 | March 11, 1987 | Siemens Aktiengesellschaft Berlin Und Munchen | Parallel connection circuit with shortened carry propagation |

EP-0214836-A1 | March 18, 1987 | Honeywell Inc. | Circuit d'addition à sélection de retenue |

EP-0328063-A2 | August 16, 1989 | Nec Corporation | Absolute value calculating circuit having a single adder |

EP-0328063-A3 | June 12, 1991 | Nec Corporation | Circuit de calcul de valeur absolue ayant un seul additionneur |

EP-0520298-A2 | December 30, 1992 | Nec Corporation | Arithmetische Schaltung |

EP-0520298-A3 | July 14, 1993 | Nec Corporation | Arithmetic circuit |

FR-2435754-A1 | April 04, 1980 | Motorola Inc | Procede et circuit d'anticipation de report |

FR-2596543-A1 | October 02, 1987 | Radiotechnique Compelec | Unite arithmetique et logique |

US-2004111455-A1 | June 10, 2004 | Micron Technology, Inc. | Hybrid arithmetic logic unit |

US-3265876-A | August 09, 1966 | Honeywell Inc | Parallel data accumulator for operating in either a binary or decimal mode |

US-3316393-A | April 25, 1967 | Honeywell Inc | Conditional sum and/or carry adder |

US-3553446-A | January 05, 1971 | Honeywell Inc | Carry determination logic |

US-3743824-A | July 03, 1973 | Rca Corp | Carry ripple network for conditional sum adder |

US-4139894-A | February 13, 1979 | U.S. Philips Corporation | Multi-digit arithmetic logic circuit for fast parallel execution |

US-4203157-A | May 13, 1980 | Motorola, Inc. | Carry anticipator circuit and method |

US-4441159-A | April 03, 1984 | International Computers Ltd. | Digital adder circuit for binary-coded numbers of radix other than a power of two |

US-4525797-A | June 25, 1985 | Motorola, Inc. | N-bit carry select adder circuit having only one full adder per bit |

US-4638449-A | January 20, 1987 | International Business Machines Corporation | Multiplier architecture |

US-4639888-A | January 27, 1987 | Siemens Aktiengesellschaft | Circuit arrangement for accelerated carry formation in an adder device |

US-4675837-A | June 23, 1987 | Siemens Aktiengesellschaft | Digital arithmetic unit having shortened processing time and a simplified structure |

US-4675838-A | June 23, 1987 | Delaware | Conditional-carry adder for multibit digital computer |

US-4704701-A | November 03, 1987 | Raytheon Company | Conditional carry adder for a multibit digital computer |

US-4707800-A | November 17, 1987 | Raytheon Company | Adder/substractor for variable length numbers |

US-4764888-A | August 16, 1988 | Motorola, Inc. | N-bit carry select adder circuit with double carry select generation |

US-4982357-A | January 01, 1991 | International Business Machines Corporation | Plural dummy select chain logic synthesis network |

US-5027311-A | June 25, 1991 | Intel Corporation | Carry select multiplexer |

US-5027312-A | June 25, 1991 | Siemens Aktiengellschaft | Carry-select adder |

US-5047974-A | September 10, 1991 | Harris Corporation | Cell based adder with tree structured carry, inverting logic and balanced loading |

US-5117386-A | May 26, 1992 | U.S. Philips Corporation | Full adder circuit |

US-5285406-A | February 08, 1994 | Advanced Micro Devices, Inc. | High speed mixed radix adder |

US-5764550-A | June 09, 1998 | Sun Microsystems, Inc. | Arithmetic logic unit with improved critical path performance |

US-7330869-B2 | February 12, 2008 | Micron Technology, Inc. | Hybrid arithmetic logic unit |